Methods and apparatuses for forming multiple radio frequency (rf) components associated with different rf bands on a chip

ABSTRACT

A device includes a first radio frequency (RF) component on a die. The first RF component includes a first lightly doped region having a first value of a characteristic, and the first RF component is configured to operate in a first RF band associated with a first frequency. The device further includes a second RF component on the die. The second RF component includes a second lightly doped region having a second value of the characteristic that is different from the first value. The second RF component is configured to operate in a second RF band associated with a second frequency that is different from the first frequency.

I. CROSS REFERENCE TO RELATED APPLICATIONS

The present application claims priority from and is a divisionalapplication of U.S. patent application Ser. No. 13/958,646 filed Aug. 5,2013, entitled “METHODS AND APPARATUSES FOR FORMING MULTIPLE RADIOFREQUENCY (RF) COMPONENTS ASSOCIATED WITH DIFFERENT RF BANDS ON A CHIP,”the content of which is incorporated by reference herein in itsentirety.

II. FIELD

The present disclosure is generally related methods and apparatuses forforming multiple radio frequency (RF) components associated withdifferent RF bands on a chip.

III. DESCRIPTION OF RELATED ART

Advances in technology have resulted in smaller and apparatuses morepowerful computing devices. For example, there currently exist a varietyof portable personal computing devices, including wireless computingdevices, such as portable wireless telephones, personal digitalassistants (PDAs), and paging devices that are small, lightweight, andeasily carried by users. More specifically, portable wirelesstelephones, such as cellular telephones and internet protocol (IP)telephones, can communicate voice and data packets over wirelessnetworks. Further, many such wireless telephones include other types ofdevices that are incorporated therein. For example, a wireless telephonecan also include a digital still camera, a digital video camera, adigital recorder, and an audio file player. Also, such wirelesstelephones can process executable instructions, including softwareapplications, such as a web browser application, that can be used toaccess the Internet. As such, these wireless telephones can includesignificant computing capabilities.

Long-term evolution (LTE) (e.g., 4G LTE) is a standard for wirelesscommunication for high-speed data. The LTE standard specifies multiplefrequency bands (e.g., multiple radio frequency (RF) bands) ranging from0.7 gigahertz (GHz) to 2.6 GHz based on geographic region. For example,devices in North America will use 700/800 megahertz (MHz) frequencybands and 1,700/1,900 MHz frequency bands, and devices in Europe willuse 800 MHz, 1,800 MHz, and 2,600 MHz frequency bands. Accordingly, fora wireless device to be compatible with multiple geographic regions, thewireless device must operate at each of the frequency bands.Additionally, the wireless device should be backwards compatible withprior standards (e.g., global system for mobile communication (GSM)standards, universal mobile telecommunications system (UMTS) standards,and wireless local area network (WLAN) standards).

To operate at multiple frequency bands, the wireless device includesmultiple RF components that are each configured to operate (meetperformance and reliability criteria) at a corresponding frequency bandof the multiple frequency bands. For example, to operate in Europe, thewireless device includes a first power amplifier (PA) configured tooperate in the 800 MHz frequency band, a second PA configured to operatein the 1,800 MHz frequency band, and a third PA configured to operate inthe 2,600 MHz frequency band.

Each RF component for a particular frequency band is typically providedon a single chip, such as a chip formed using gallium arsenide (GaAs) orindium gallium phosphide (InGaP) chips. Accordingly, the wireless deviceincludes multiple chips, each with different frequency-band-specificdevices, to operate at multiple frequency bands. The use of multiplechips is expensive, requires a large footprint (e.g., printed circuit(PC) board area), and increases a size of the wireless device.

IV. SUMMARY

The present disclosure provides methods of performing a complementarymetal-oxide-semiconductor (CMOS) process on a wafer (e.g., a die) toform multiple radio frequency (RF) circuits (e.g., a first RF circuitand a second RF circuit) that each operate at different RF bands. Forexample, the wafer may include a silicon on insulator (SOI) wafer, asilicon on silicon (SOS) wafer, or a bulk silicon wafer. Each of the RFcircuits may include a receiver, a transmitter, or a combinationthereof. For example, a first RF circuit may be designed to operate at afirst RF band, and a second RF circuit may be designed to operate at asecond RF band. The CMOS process may include forming, on the first RFcircuit, a first RF device having a first device type and a firstcharacteristic and forming a second RF device having a second devicetype and a second characteristic on the second RF circuit. The first RFdevice and the second RF device are the same type of device (i.e., havea same device type), such as a power amplifier, an antenna switch, or alow noise amplifier. Additionally, the first characteristic and thesecond characteristic are the same type of characteristic (i.e., samecharacteristic type), such as an oxide thickness, a lightly doped regionprofile, or a halo profile. However, a value of the first characteristicis different than a value of the second characteristic. For example,when the characteristic type is an oxide thickness, a first oxidethickness of the first device may be thicker than a second oxidethickness of the second device. The value of the first characteristicmay be determined to enable the first RF circuit to operate at the firstRF band, and the value of the second characteristic may be determined toenable the second RF circuit to operate at the second RF band.

In a particular embodiment, a method includes forming a first gate oxidein a first region and in a second region of a wafer. The method furtherincludes performing first processing to form a second gate oxide in thesecond region. The second gate oxide has a different thickness than thefirst gate oxide. The method also includes forming first gate materialof a first device in the first region and forming second gate materialof a second device in the second region. The first device corresponds toa first radio frequency (RF) band, and the second device corresponds toa second RF band that is different from the first RF band.

In a particular embodiment, a device includes a first radio frequency(RF) component and a second RF component on a die. The first RFcomponent corresponds to a first RF band, and the second RF componentcorresponds to a second RF band that is different from the first RFband. The first RF component includes a first gate oxide having a firstthickness, and the second RF component includes a second gate oxidehaving a second thickness that is different from the first thickness.

In a further particular embodiment, an apparatus includes a first radiofrequency (RF) component corresponding to a first RF band, and a secondRF component corresponding to a second RF band that is different fromthe first RF band. The first RF component includes first means forgating a first channel. The first channel is positioned between firstmeans for sourcing first current to the first channel and first meansfor draining the first current from the first channel. The means forgating the channel is isolated from first semiconductor means forconducting first charge carriers by a first insulator. The second RFcomponent includes second means for gating a second channel. The secondchannel is positioned between second means for sourcing second currentto the second channel and second means for draining the second currentfrom the second channel. The second means for gating the second channelis isolated from second semiconductor means for conducting second chargecarriers by a second insulator. A first thickness of the first insulatoris different than a second thickness of the second insulator.

In another particular embodiment, a non-transitory computer-readablemedium includes instructions that, when executed by a processor, causethe processor to initiate formation of a complementarymetal-oxide-semiconductor (CMOS) device. The formation of the CMOSdevice includes forming a first gate oxide in a first region and in asecond region of a wafer. The CMOS device is further formed byperforming first processing to form a second gate oxide in the secondregion. The second gate oxide has a different thickness than the firstgate oxide. The formation of the CMOS device also includes forming firstgate material of a first device in the first region and forming secondgate material of a second device in the second region. The first devicecorresponds to a first radio frequency (RF) band, and the second devicecorresponds to a second RF band that is different from the first RFband.

In another particular embodiment, a device includes a first radiofrequency (RF) component and a second RF component on a die. The firstRF component corresponds to a first RF band, and the second RF componentcorresponds to a second RF band that is different from the first RFband. The first RF component includes a first lightly doped regionhaving a first value of a characteristic, and the second RF componentincludes a second lightly doped region having a second value of thecharacteristic that is different from the first value.

In another particular embodiment, a device includes a first radiofrequency (RF) component and a second RF component on a die. The firstRF component corresponds to a first RF band, and the second RF componentcorresponds to a second RF band that is different from the first RFband. The first RF component includes a first halo region having a firstvalue of a characteristic, and the second RF component includes a secondhalo region having a second value of the characteristic that isdifferent from the first value.

In another particular embodiment, a method includes a first step forforming a first gate oxide in a first region and in a second region of awafer. The method further includes a second step for performing firstprocessing to form a second gate oxide in the second region, the secondgate oxide having a different thickness than the first gate oxide. Themethod also includes a third step for forming first gate material of afirst device in the first region and forming second gate material of asecond device in the second region. The first device corresponds to afirst radio frequency (RF) band, and the second device corresponds to asecond RF band that is different from the first RF band.

In another particular embodiment, a method includes performing, on awafer, a complementary metal-oxide-semiconductor (CMOS) process to forma first radio frequency (RF) circuit and a second RF circuit. The firstRF circuit is designed to operate at a first RF band and the second RFcircuit is designed to operate at a second RF band. Performing the CMOSprocess includes forming a first RF device of the first RF circuit andforming a second RF device of the second RF circuit. The first RF devicehas a first device type and a first value of a characteristic, and thesecond RF device has a second device type and a second value of thecharacteristic. The first device type and the second device type are asame device type, and the first value of the characteristic is differentfrom the second value of the characteristic.

In another particular embodiment, a method includes receiving designinformation representing at least one physical property of asemiconductor device. The semiconductor device includes a first radiofrequency (RF) component and a second RF component on a die. The firstRF component corresponds to a first RF band, and the second RF componentcorresponds to a second RF band that is different from the first RFband. The first RF component includes a first gate oxide having a firstthickness, and the second RF component includes a second gate oxidehaving a second thickness that is different from the first thickness.The method further includes transforming the design information tocomply with a file format and generating a data file including thetransformed design information.

One particular advantage provided by at least one of the disclosedembodiments is that a single die may advantageously include multiple RFband circuits that are each designed for performance and reliability ata corresponding frequency band. The die may have a smaller form factorand may be produced at a reduced cost as compared to including a RFcircuit on a separate chip for each frequency band.

Other aspects, advantages, and features of the present disclosure willbecome apparent after review of the entire application, including thefollowing sections: Brief Description of the Drawings, DetailedDescription, and the Claims.

V. BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a first illustrative embodiment of a devicehaving a die that accommodates multiple radio frequency (RF) bands;

FIGS. 2A-B are block diagrams of illustrative embodiments ofcomplementary metal-oxide-semiconductor (CMOS) devices that accommodatemultiple RF bands;

FIG. 3 is a flow diagram of an illustrative embodiment of a first methodto form a die that accommodates multiple RF bands;

FIG. 4 is a flow diagram of an illustrative embodiment of a secondmethod to form a die that accommodates multiple RF bands;

FIG. 5 is a flow diagram of an illustrative embodiment of a third methodto form a die that accommodates multiple RF bands;

FIG. 6 is a block diagram of a device including the die of FIG. 1; and

FIG. 7 is a data flow diagram of an illustrative embodiment of amanufacturing process including the die of FIG. 1.

VI. DETAILED DESCRIPTION

Particular embodiments of the present disclosure are described belowwith reference to the drawings. In the description, common features aredesignated by common reference numbers throughout the drawings.

Referring to FIG. 1, a device 100 (e.g., a communication device) thataccommodates multiple radio frequency (RF) bands is shown. The device100 includes a die 102 having multiple RF circuits, such as a first RFband circuit 110, a second RF band circuit 120, an Nth RF band circuit130, and additional circuitry 140. The die 102 may be packaged in (e.g.,incorporated in) a chip, such as a semiconductor chip. Although the die102 is shown as including the additional circuitry 140, the additionalcircuitry 140 may be coupled to the die 102 but not be included in thedie 102. The device 100 may include a communication device, such as aportable communication device) configured for RF communication. Thedevice 100 may include one or more additional components or circuits(not shown), such as a processor (e.g., a digital signal processor), awireless transceiver, a memory, an antenna, one or more othercomponents, or a combination thereof.

The multiple RF circuits 110, 120, 130, the additional circuitry 140, ora combination thereof, may be formed by a front end process, such as afront end complementary metal-oxide-semiconductor (CMOS) process. Thefront end process may be performed with respect to a wafer (e.g., fromwhich the die 102 is created), as described further herein. As a resultof the front end process, the die 102 includes multiple RF circuits(e.g., the first RF band circuit 110, the second RF band circuit 120,the Nth RF band circuit 130), and the additional circuitry 140 (e.g.,control circuitry). Although the die 102 shows three different RF bandcircuits 110, 120, 130, the die 102 may include two RF band circuits ormore than three RF band circuits.

Each of the RF band circuits 110, 120, 130 may include one or morecomponents. For example, the first RF band circuit 110 may include afirst device 112, the second RF band circuit 120 may include a seconddevice 122, and the Nth RF band circuit 130 may include an Nth device132. Each of the first device 112, the second device 122, and the Nthdevice may be a same device type, such as a power amplifier, an antennaswitch, or a low noise amplifier and may be constructed during a singlefront end process flow. Each of the RF band circuits 110, 120, 130 maycorrespond to a different RF band. For example, each of the RF bandcircuits 110, 120, 130 may be designed to operate at a different RF bandand within a corresponding electrical domain of operation as compared tothe others of the RF band circuits 110, 120, and 130. The first RF bandcircuit 110 may be designed to operate at a lower RF band than thesecond RF band circuit 120. Accordingly, each of the devices 112, 122,132 may be designed (e.g., optimized) to operate at the RF band, theelectrical domain of operation, or a combination thereof, correspondingto the RF band circuit 110, 120, 130 that includes the device 112, 122,or 132. Each of the devices 112, 122, 132 may be configured with adifferent value of a same characteristic (e.g., a characteristic type),such as described further with reference to FIGS. 2A-B. For example, thedevices 112, 122, 132 may have different values of an oxide thickness(e.g., a gate oxide thickness), different values associated with alightly doped region profile, different values associated with a haloprofile, or a combination thereof. For example, the first device 112 mayhave a first oxide thickness, the second device 122 may have a secondoxide thickness different from the first oxide thickness, and the Nthdevice 132 may have a third oxide thickness that is different from thefirst oxide thickness and the second oxide thickness.

The additional circuitry 140 may be coupled to each of the RF bandcircuits 110, 120, 130. The additional circuitry 140 may be configuredto operate the device 100 in different modes, such as differentcombinations of frequency bands. For example, the additional circuitry140 may be configured to select one or more of the RF band circuits 110,120, 130 of the device 100 for operation based on particularcircumstances.

For example, during operation of the device 100, the additionalcircuitry 140 may determine or receive an indication (e.g., from aprocessor or positioning system of the device 100) of the geographiclocation in which the device 100 is located. Based on the geographiclocation, the additional circuitry 140 may selectively activate (e.g.,enable to operate) or deactivate one or more of the RF band circuits110, 120, 130. Alternatively, one or more of the RF band circuits 110,120, 130 may be selected for operation based on other criteria, such asprogrammable settings.

During operation, the additional circuitry 140 may determine that thedevice 100 is located in North America, which uses 700/800 MHz frequencybands and 1,700/1,900 MHz frequency bands. Based on the device 100 beinglocated in North America, the additional circuitry 140 may selectivelyactivate, deactivate, or a combination thereof, one or more of the RFband circuits 110, 120, 130 to enable the device 100 to operate at the700/800 MHz frequency bands and the 1,700/1,900 MHz frequency bands.After the device 100 is configured to operate in North America, theadditional circuitry 140 may determine that the device is located inEurope (e.g., if a user of a wireless phone travels from North Americato Europe), which uses 800 MHz, 1,800 MHz, and 2,600 MHz frequencybands. Based on the device 100 being located in Europe, the additionalcircuitry 140 may selectively activate, deactivate, or a combinationthereof, one or more of the RF band circuits 110, 120, 130 to enable thedevice 100 to operate at the 800 MHz, 1,800 MHz, and 2,600 MHz frequencybands.

The die 102 of device 100 may advantageously include multiple RF bandcircuits 110, 120, 130 that are each designed for performance andreliability at a corresponding frequency band. The device 100 may have asmaller form factor and may be produced at a reduced cost as compared tousing multiple RF circuits that are constructed on multiple dies.

Referring to FIGS. 2A-B, illustrative embodiments of complementarymetal-oxide-semiconductor (CMOS) devices that accommodate multiple RFbands are disclosed. The CMOS devices may include a silicon on insulator(SOI) CMOS device, a silicon on silicon (SOS) CMOS device, or a bulksilicon CMOS device. FIG. 2A illustrates a first CMOS device 200 that isa silicon on insulator (SOI) CMOS device. FIG. 2B illustrates a secondCMOS device 290 that is a bulk silicon CMOS device. One or more dies,such as the die 102 of FIG. 1, may be created from the first CMOS device200 or the second CMOS device 290.

Referring to FIG. 2A, the first CMOS device 200 includes a wafer 202onto which a first device 240 and a second device 260 are formed. Thefirst device 240 may be associated with a first radio frequency (RF)band and the second device 260 may be associated with a second RF band.For example, the first device 240 and the second device 260 may eachcorrespond to a different one of the devices 112, 122, 132 of FIG. 1.Although each of the first device 240 and the second device 260 isillustrated as a single transistor for ease of explanation, the firstdevice 240 and the second device 260 are not limited to a singletransistor. For example, each of the first device 240 and the seconddevice 260 may be a same device type, such as a power amplifier, anantenna switch, or a low noise amplifier, and may be constructed duringa single front end process flow. Each of the first device 240 and thesecond device 260 may be designed to operate at a different RF band andwithin a corresponding electrical domain of operation. A dashed line 224illustrates a representative logical division of the first CMOS device200 into a first portion and a second portion. One of skill in the artwill appreciate that although the first CMOS device 200 depicts twodevices 240, 260, the first CMOS device 200 may include more than twodevices.

The first CMOS device 200 may include a substrate 204, an insulatormaterial 206 (e.g., a dielectric insulator), and a semiconducting layer208 (e.g., a semiconductor layer, such as a silicon (Si) layer). In aparticular embodiment, the substrate 204 includes silicon (Si), theinsulator material 206 may include a buried oxide (BOX), and thesemiconducting layer 208 may include silicon (Si). In a particularembodiment, the substrate 204, the insulator material 206, and thesemiconducting layer 208 are included in the wafer 202.

The insulator material 206, the semiconducting layer 208, or acombination thereof, may include a first region 241 corresponding to thefirst device 240 and a second region 261 corresponding to the seconddevice 260. The insulator material 206 of the first region 241 may havea first insulator material thickness t_(I1) and the insulator material206 of the second region 261 may have a second insulator materialthickness t_(I2). The first insulator material thickness t_(I1) and thesecond insulator material thickness t_(I2) may be the same thickness ordifferent thicknesses. The semiconducting layer 208 of the first region241 may have a first semiconducting layer thickness t_(Si1) and thesemiconducting layer 208 of the second region 261 may have a secondsemiconducting layer thickness t_(Si2). The first semiconducting layerthickness t_(Si1) and the second semiconducting layer thickness t_(Si2)may be the same thickness or different thicknesses.

The first region 241 and the second region 261 may be separated by ashallow trench isolation (STI) region 222. Each of the first region 241and the second region 261 may include source/drain (S/D) implants 210and a well region 212. Either S/D implant 210 of the first device 240and either S/D implant 210 of the second device 260 may be associatedwith a source or associated with a drain of the correspondingtransistor, as long as the first device 240 has a source and a drain andthe second device 260 has a source and a drain.

The first device 240 may include a first gate 242 and a first gate oxide244. The first gate 242 and the first gate oxide 244 may be positionedabove a first channel region of the semiconducting layer 208 of thefirst region 241. The first gate 242 may define a first channel lengthL_(g1), and the first gate oxide 244 may have a height h₁ (e.g., a firstgate oxide thickness). The first gate 242, the first gate oxide 244, ora combination thereof, may have first spacers 250 attached thereto. Forexample, the first spacers 250 may be formed on the first gate 242. Thefirst spacers 250 may have a first spacer thickness t_(S1) and a firstspacer profile (e.g., a volume, a cross sectional area, or a crosssectional shape). The first device 240 may further include a firstlightly doped region 246 (e.g., a lightly doped implant) and a firsthalo region 248 (e.g., a halo implant). The first lightly doped region246 and the first halo region 248 may be included within the well region212 of the first region 241. The first lightly doped region 246 mayinclude a first lightly doped characteristic. The first lightly dopedcharacteristic may include a first lightly doped profile (e.g., avolume, a cross sectional area, or a cross sectional shape of the firstlightly doped region 246), a first lightly doped dopant type, a firstlightly doped dopant concentration, or a combination thereof. The firsthalo region 248 may include a first halo characteristic. The first halocharacteristic may include a first halo profile (e.g., a volume, a crosssectional area, or a cross sectional shape of the first halo region248), a first halo dopant type, a first halo dopant concentration, or acombination thereof.

The second device 260 may include a second gate 262 and a second gateoxide 264. The second gate 262 and the second gate oxide 264 may bepositioned above a second channel region of the semiconducting layer 208of the second region 261. The second gate 262 may define a secondchannel length L_(g2), and the second gate oxide 264 may have a heighth₂ (e.g., a second gate oxide thickness). The second gate 262, thesecond gate oxide 264, or a combination thereof, may have second spacers270 attached thereto. For example, the second spacers 270 may be formedon the second gate 262. The second spacers 270 may have a second spacerthickness t_(S2) and a second spacer profile (e.g., a volume, a crosssectional area, or a cross sectional shape). The second device 260 mayfurther include a second lightly doped region 266 and a second haloregion 268. The second lightly doped region 266 and the second haloregion 268 may be included within the well region 212 of the secondregion 261. The second lightly doped region 266 may include a secondlightly doped characteristic. The second lightly doped characteristicmay include a second lightly doped profile (e.g., a volume, a crosssectional area, or a cross sectional shape of the second lightly dopedregion 266), a second lightly doped dopant type, a second lightly dopeddopant concentration, or a combination thereof. The second halo region268 may include a second halo characteristic. The second halocharacteristic may include a second halo profile (e.g., a volume, across sectional area, or a cross sectional shape of the second haloregion 268), a second halo dopant type, a second halo dopantconcentration, or a combination thereof.

Values of one or more characteristics of the first device 240 and thesecond device 260 may differ based on the corresponding frequency bandof the first device 240 and the second device 260. For example, thefirst channel length L_(g1) of the first gate 242 may be the same lengthor a different length than the second channel length L_(g2) of thesecond gate 262. The height h₁ of the first gate oxide 244 may be thesame height or a different height as the height h₂ of the second gateoxide 264. The first spacer thickness t_(S1) of the first spacers 250may be the same thickness or a different thickness than the secondspacer thickness t_(S2) of the second spacers 270. A value of the firstlightly doped characteristic of the first lightly doped region 246 maybe the same as or different than a corresponding value of the secondlightly doped characteristic of the second lightly doped region 266. Avalue of the first halo characteristic of the first halo region 248 maybe the same as or different than a corresponding value of the secondhalo characteristic of the second halo region 268.

Referring to FIG. 2B, the second CMOS device 290 includes a wafer 292onto which the first device 240 and the second device 260 are formed.The wafer 292 may include a substrate 294, such as silicon. Thesubstrate 294 may include a first region 241 corresponding to the firstdevice 240 and a second region 261 corresponding to the second device260. The substrate 294 may include the STI regions 222, the S/D implants210, the first lightly doped region 246, the first halo region 248, thesecond lightly doped regions 266, and the second halo region 268.

Referring to FIGS. 2A-B, the first device 240 and the second device 260are a same device type, and each of first device 240 and the seconddevice 260 is designed to operate at a different RF band and within adifferent corresponding electrical domain of operation. For example, thefirst device 240 may be designed to operate at a lower RF band than thesecond device 260. Accordingly, the first device 240 may be referred toas a low band device, and the second device 260 may be referred to as ahigh band device. In a particular embodiment, the first device 240 is alow band power amplifier, and the second device 260 is a high band poweramplifier.

When the first device 240 is the low band device and the second device260 is the high band device, one or more attributes (e.g., one or morecharacteristic values) of the first device 240 and the second device 260may be determined based on the frequency band in which each device isdesigned to operate. As a first example, the first insulator materialthickness t_(I1) may be thicker than the second insulator materialthickness t_(I2). As a second example, the first semiconducting layerthickness t_(Si1) may be thicker than the second semiconducting layerthickness t_(Si12). As a third example, the first channel length L_(g1)of the first gate 242 may be longer than the second channel lengthL_(g2) of the second gate 262. As a fourth example, the height h₁ of thefirst gate oxide 244 may be larger (e.g., thicker) than the height h₂ ofthe second gate oxide 264. As a fifth example, the first spacerthickness t_(S1) of the first spacers 250 may be thicker than the secondspacer thickness t_(S2) of the second spacers 270. As a sixth example, afirst cross sectional area of the first spacer profile of the firstspacers 250 may be larger than a second cross sectional area of thesecond spacer profile of the second spacers 270.

As a seventh example, a first cross sectional area of the first lightlydoped profile of the first lightly doped region 246 may be larger than asecond cross sectional area of the second lightly doped profile of thesecond lightly doped region 266. As an eighth example, the first lightlydoped dopant type of the first lightly doped region 246 may be a firstlightly doped dopant having a larger molecular mass (e.g., molecularweight) than a second lightly doped dopant of the second lightly dopeddopant type of the second lightly doped region 266. As a ninth example,the first lightly doped dopant concentration of the first lightly dopedregion 246 may be a greater dopant concentration (e.g., a dopingconcentration) than the second lightly doped dopant concentration of thesecond lightly doped region 266.

As a tenth example, a first cross sectional area of the first haloprofile of the first halo region 248 may be larger than a second crosssectional area of the second halo profile of the second halo region 268.As an eleventh example, the first halo dopant type of the first haloregion 248 may be a first halo dopant having a larger molecular mass(e.g., molecular weight) than a second halo dopant of the second halodopant type of the second halo region 268. As a twelfth example, thefirst halo dopant concentration (e.g., a doping concentration) of thefirst halo region 248 may be a greater dopant concentration than thesecond halo dopant concentration of the second halo region 268.

One or more of the examples described above may be incorporated in orotherwise utilized by the first CMOS device 200 of FIG. 2A or the secondCMOS device 290 of FIG. 2B based on the RF bands for the first region241 and the second region 261. Thus, a single die of the first CMOSdevice 200 of FIG. 2A or the second CMOS device 290 of FIG. 2B mayadvantageously include multiple RF devices that are each designed forperformance and reliability at a corresponding frequency band. The firstCMOS device 200 of FIG. 2A or the second CMOS device 290 of FIG. 2B mayhave a smaller form factor and may be produced at a reduced cost ascompared to RF circuits that are constructed on separate wafers orseparate chips. Examples of forming/fabricating a semiconductor device,such as the first CMOS device 200 of FIG. 2A or the second CMOS device290 of FIG. 2B, are described with reference to FIGS. 3-5.

Referring to FIG. 3, a first illustrative embodiment of a method 300 toform a single die that accommodates multiple RF bands is illustrated.The single die may be formed by a complementarymetal-oxide-semiconductor (CMOS) process performed on a wafer. Forexample, the single die may include the die 102 of FIG. 1, a die of thefirst CMOS device 200 of FIG. 2A, or a die of the second CMOS device 290of FIG. 2B.

A first radio frequency (RF) device of a first RF circuit is formed, at302. The first RF device has a first device type (e.g., first componenttype) and a first value of a characteristic. The first RF circuit isdesigned to operate at a first RF band. For example, the first RF devicemay correspond to or be associated with one of the devices 112, 122, 132of FIG. 1 or one of the first device 240 or the second device 260 ofFIGS. 2A-B.

A second RF device of a second RF circuit is formed, at 304. The secondRF device has a second device type (e.g., a second component type) and asecond value of the characteristic. For example, the second RF devicemay correspond to or be associated with one of the devices 112, 122, 132of FIG. 1 or one of the first device 240 or the second device 260 ofFIGS. 2A-B. The second RF circuit is designed to operate at a second RFband. The first device type and the second device type are a same devicetype (e.g., a same component type). The first value of thecharacteristic is different than the second value of the characteristic.The first RF circuit and the second RF circuit are formed by acomplementary metal-oxide-semiconductor (CMOS) process performed on awafer, such as a silicon on insulator (SOI) wafer, a silicon on silicon(SOS) wafer, or a bulk silicon wafer.

Thus, a method of forming a single chip that accommodates multiple RFbands has been described. The first device and the second device aredesigned to operate at different RF bands. For example, the first devicemay be designed to operate at a first frequency band, and the seconddevice may be designed to operate at a second frequency band. In aparticular embodiment, the first frequency band is a lower frequencyband than the second frequency band. Each device may be configured basedon a corresponding frequency band by adjusting one or more parameters(e.g., one or more characteristic values) of the device, such as achannel length, a gate oxide thickness, a lightly doped region profilevolume or cross sectional area, a halo region profile volume or crosssectional area, a silicon layer thickness, a buried oxide layerthickness, or a spacer thickness during the CMOS process, as describedfurther with reference to FIGS. 4 and 5.

Referring to FIG. 4, a second illustrative embodiment of a method toform a single die that accommodates multiple RF bands is illustrated anddesignated 400. For example, the single die may include the die 102 ofFIG. 1, a die of the first CMOS device 200 of FIG. 2A, or a die of thesecond CMOS device 290 of FIG. 2B.

First processing is performed on a first region and a second region, at402. The first processing may be configured to construct (e.g.,fabricate) a first device to operate at a first RF band and to constructa second device to operate at a second RF band. For example, the firstdevice and the second device may each be associated with a different oneof the devices 112, 122, 132 of FIG. 1 or the first device 240 and thesecond device 260 of FIGS. 2A-B.

The first processing may include forming a first gate oxide on the die,at 404, and the first processing may include performing secondprocessing to form a second gate oxide on the second region, at 406. Thefirst gate oxide may be formed on the first region (e.g., the firstregion 241 of FIGS. 2A-B) and on the second region (e.g., the secondregion 261 of FIGS. 2A-B). The second processing may include performingthin gate lithography to cover (e.g., protect) the first gate oxide inthe first region and to expose (e.g., leave uncovered) the first gateoxide on the second region, removing the first gate oxide from thesecond region, and forming the second gate oxide on the second region(e.g., the second gate oxide 264 in the second region 261). Accordingly,the second gate oxide may have a different thickness than the first gateoxide. For example, when the first device is configured to operate at alower frequency than the second device, the first gate oxide may bethicker than the second gate oxide. Alternatively, the second processingmay include performing thin gate lithography to cover (e.g., protect)the first gate oxide in the first region and to expose (e.g., leaveuncovered) the first gate oxide on the second region and forming thesecond gate oxide on the second region by adding additional gate oxidematerial to the first gate oxide in the first region.

First gate material of a first device may be formed on the first region,and second gate material of a second device may be formed on the secondregion, at 408. To illustrate, polysilicon may be formed over the gateoxide in both regions in a common depositing/lithography/etchingprocess. For example, the first device may correspond to one of thefirst device 112, the second device 122, and the Nth device 132 of FIG.1, or the first device 240 and the second device 260 of FIGS. 2A-B, andthe second device may correspond to another one of the first device 112,the second device 122, and the Nth device 132 of FIG. 1, or the firstdevice 240 and the second device 260 of FIGS. 2A-B. The first device andthe second device may each be designed to operate at different radiofrequency bands. For example, the first device may correspond to a firstradio frequency (RF) band, and the second device may correspond to asecond RF band that is different from the first RF band. In a particularembodiment, the first device is a first power amplifier and the seconddevice is a second power amplifier.

Referring to FIG. 5, a third illustrative embodiment of a method to forma single die that accommodates multiple RF bands is illustrated anddesignated 500. For example, the single die may include the die 102 ofFIG. 1. The method may include a complementary metal-oxide-semiconductor(CMOS) process.

Common processing steps may be performed on a wafer, at 502. The wafer,such as a silicon on insulator (SOI) wafer, a silicon on silicon (SOS)wafer, or a bulk silicon wafer, may include a first region and a secondregion, such as the first region 241 and the second region 261 of FIGS.2A-B. The first region may be associated with a first device designed tooperate at a first RF band, and the second region may be associated witha second device designed to operate at a second RF band. For example,the first device may correspond to one of the first device 112, thesecond device 122, and the Nth device 132, of FIG. 1, or the firstdevice 240 and the second device 260 of FIGS. 2A-B, and the seconddevice may correspond to another one of the first device 112, the seconddevice 122, and the Nth device 132, of FIG. 1, or the first device 240and the second device 260 of FIGS. 2A-B. The first device and the seconddevice may each be designed to operate at different radio frequencybands. In a particular embodiment, the first device is a first poweramplifier, and the second device is a second power amplifier. The wafermay include the wafer 202 of FIG. 2A, such as a silicon on insulatorwafer having a substrate layer, an insulator material layer, and asemiconducting layer (e.g., a silicon layer) or may include the wafer292 of FIG. 2B, such as a bulk silicon wafer. The common processing mayinclude forming shallow trench isolation regions, p well regions, n wellregions, one or more other semiconductor process components, or acombination thereof.

Wafer processing may be performed on the wafer prior to performing thecommon processing. For example, the wafer processing may includeconfiguring a first thickness of the silicon layer of the first regionto be thicker than a second thickness of the silicon layer of the secondregion when the first device is designed to operate at a lower RF bandthan the second device. As another example, when the first device isdesigned to operate at a lower RF band than the second device, the waferprocessing may include configuring a first thickness of the buried oxidelayer of the first region to be thicker than a second thickness of theburied oxide layer of the second region.

A first gate oxide may be formed on the first region, and a second gateoxide may be formed on the second region, at 504. The first gate oxideand the second gate oxide may have a same or a different thickness. Thefirst oxide (e.g., a thickness of the first oxide) may be configured toenable the first device to operate in a first electrical domain ofoperation corresponding to a first RF band, and the second oxide (e.g.,a thickness of the second oxide) may be configured to enable the seconddevice to operate in a second electrical domain of operationcorresponding to a second RF band. For example, the first gate oxide andthe second gate oxide may be formed according to at least a portion ofthe method 400 of FIG. 4.

First gate material of the first device may be formed on the firstregion, and second gate material of the second device may be formed onthe second region, at 508. For example, the first gate material and thesecond gate material may be formed during a common gate formationprocess performed on the first region and the second region.

Processing is performed on a first region and a second region, at 510.The processing may construct (e.g., fabricate) the first device tooperate at the first RF band and to construct the second device tooperate at the second RF band. The processing may include performingfirst processing on the first region, at 512, and performing secondprocessing on the second region, at 514. The first processing and thesecond processing may correspond to a same characteristic type of thefirst device and the second device. For example, the characteristic typemay include a channel length, a gate oxide thickness, a lightly dopedregion characteristic, a halo region characteristic, or a combinationthereof. A first value of the characteristic type of the first devicemay be different than a second value of the characteristic type of thesecond device. For example, when the first device is designed to operateat a lower RF band than the second device, a first channel length of thefirst device may be longer than a second channel length of the seconddevice, a first gate oxide thickness of the first device may be thickerthan a second gate oxide thickness of the second device, a first lightlydoped region characteristic (e.g., a profile volume, a profile crosssectional area, a profile cross sectional shape, a dopant concentration,or a dopant type) of the first device may be different than a secondlightly doped region characteristic of the second device, a first haloregion characteristic (e.g., a profile volume, a profile cross sectionalarea, a profile cross sectional shape, a dopant concentration, or adopant type) of the first device may be greater than a second haloregion characteristic of the second device, or a combination thereof.

Second common processing may be performed on the first region and thesecond region, at 516. The second common processing may include formingspacers, forming n source/drain implants, p source/drain implants,silicides, contacts, metal 1 layers, vias, metal 2 layers, or acombination thereof.

The method 300 of FIG. 3, the method 400 of FIG. 4, the method 500 ofFIG. 5, or any combination thereof, may be initiated or controlled by afield-programmable gate array (FPGA) device, an application-specificintegrated circuit (ASIC), a processing unit, such as a centralprocessing unit (CPU), a digital signal processor (DSP), a controller,another hardware device, a firmware device, or any combination thereof.As an example, the method 300 of FIG. 3, the method 400 of FIG. 4, orthe method 500 of FIG. 5 can be initiated or controlled by one or moreprocessors, operating systems, or controllers.

Referring to FIG. 6, a block diagram of a particular illustrativeembodiment of a wireless communication device 600 is depicted. Thedevice 600 may include, or have incorporated therein, the die 102 ofFIG. 1.

The device 600 includes a processor 610, such as a digital signalprocessor (DSP), coupled to a memory 632. The memory 632 includesinstructions 668 (e.g., executable instructions) such ascomputer-readable instructions that are readable by the processor 610.The instructions 668 may include one or more instructions that areexecutable by a computer, such as the processor 610.

FIG. 6 also shows a display controller 626 that is coupled to theprocessor 610 and to a display 628. A coder/decoder (CODEC) 634 can alsobe coupled to the processor 610. A speaker 636 and a microphone 638 canbe coupled to the CODEC 634.

FIG. 6 also indicates that a wireless interface 640 can be coupled tothe processor 610 and to an antenna 642. The wireless interface 640 mayinclude a wireless controller, a wireless transceiver, such as areceiver circuit, a transmitter circuit, or a combination thereof. Thewireless interface 640 may include a device 664, such as the die 102 ofFIG. 1. For example, the device 664 may include a first radio frequency(RF) component and a second RF component, such as the first device 112and the second device 122 of FIG. 1. For example, the first RF componentand the second RF component may each include a power amplifier, anantenna switch, a low noise amplifier, or one or more transistors.Accordingly, the first RF component and the second RF component may beincluded in a receiver circuit, a transmitter circuit, or a combinationthereof. The device 664 may be a chip (e.g., a single chip) configuredto accommodate multiple radio frequency (RF) bands. In an alternativeembodiment, the device 664 may be located in one or more components ofthe device 600 other than in the wireless interface 640.

In a particular embodiment, the processor 610, the display controller626, the memory 632, the CODEC 634, and the wireless interface 640 areincluded in a system-in-package or system-on-chip device 622. In aparticular embodiment, an input device 630 and a power supply 644 arecoupled to the system-on-chip device 622. Moreover, in a particularembodiment, as illustrated in FIG. 6, the display 628, the input device630, the speaker 636, the microphone 638, the wireless antenna 642, andthe power supply 644 are external to the system-on-chip device 622.However, each of the display 628, the input device 630, the speaker 636,the microphone 638, the antenna 642, and the power supply 644 can becoupled to a component of the system-on-chip device 622, such as aninterface or a controller.

One or more of the disclosed embodiments may be implemented in a systemor an apparatus, such as the device 600, that may include acommunications device, a fixed location data unit, a mobile locationdata unit, a mobile phone, a cellular phone, a satellite phone, acomputer, a tablet, a portable computer, or a desktop computer.Additionally, the device 600 may include a set top box, an entertainmentunit, a navigation device, a personal digital assistant (PDA), amonitor, a computer monitor, a television, a tuner, a radio, a satelliteradio, a music player, a digital music player, a portable music player,a video player, a digital video player, a digital video disc (DVD)player, a portable digital video player, any other device that stores orretrieves data or computer instructions, or a combination thereof. Asanother illustrative, non-limiting example, the system or the apparatusmay include remote units, such as mobile phones, hand-held personalcommunication systems (PCS) units, portable data units such as personaldata assistants, global positioning system (GPS) enabled devices,navigation devices, fixed location data units such as meter readingequipment, or any other device that stores or retrieves data or computerinstructions, or any combination thereof.

The foregoing disclosed devices and functionalities may be designed andconfigured into computer files (e.g. RTL, GDSII, GERBER, etc.) stored oncomputer-readable media. Some or all such files may be provided tofabrication handlers who fabricate devices based on such files.Resulting products include semiconductor wafers that are then cut intosemiconductor die and packaged into a semiconductor chip. The chips arethen employed in devices described above. FIG. 7 depicts a particularillustrative embodiment of an electronic device manufacturing process700.

Physical device information 702 is received at the manufacturing process700, such as at a research computer 706. The physical device information702 may include design information representing at least one physicalproperty of a semiconductor device, such as a semiconductor deviceincluding the die 102 of FIG. 1. For example, the physical deviceinformation 702 may include physical parameters, materialcharacteristics, and structure information that is entered via a userinterface 704 coupled to the research computer 706. The researchcomputer 706 includes a processor 708, such as one or more processingcores, coupled to a computer-readable medium such as a memory 710. Thememory 710 may store computer-readable instructions that are executableto cause the processor 708 to transform the physical device information702 to comply with a file format and to generate a library file 712.

In a particular embodiment, the library file 712 includes at least onedata file including the transformed design information. For example, thelibrary file 712 may include a library of semiconductor devicesincluding a device that includes the die 102 of FIG. 1, that is providedto use with an electronic design automation (EDA) tool 720.

The library file 712 may be used in conjunction with the EDA tool 720 ata design computer 714 including a processor 716, such as one or moreprocessing cores, coupled to a memory 718. The EDA tool 720 may bestored as processor-executable instructions at the memory 718 to enablea user of the design computer 714 to design a circuit including the die102 of FIG. 1, of the library file 712. For example, a user of thedesign computer 714 may enter circuit design information 722 via a userinterface 724 coupled to the design computer 714. The circuit designinformation 722 may include design information representing at least onephysical property of a semiconductor device, such as a semiconductordevice that includes the die 102 of FIG. 1. To illustrate, the circuitdesign property may include identification of particular circuits andrelationships to other elements in a circuit design, positioninginformation, feature size information, interconnection information, orother information representing a physical property of a semiconductordevice.

The design computer 714 may be configured to transform the designinformation, including the circuit design information 722, to complywith a file format. To illustrate, the file formation may include adatabase binary file format representing planar geometric shapes, textlabels, and other information about a circuit layout in a hierarchicalformat, such as a Graphic Data System (GDSII) file format (e.g., a GDSIIformat). The design computer 714 may be configured to generate a datafile including the transformed design information, such as a GDSII file726 that includes information describing the die 102 of FIG. 1, inaddition to other circuits or information. To illustrate, the data filemay include information corresponding to a system-on-chip (SOC) thatincludes the die 102 of FIG. 1, and that may also include additionalelectronic circuits and components within the SOC.

The GDSII file 726 may be received at a fabrication process 728 tomanufacture a wafer including the die 102 of FIG. 1, according totransformed information in the GDSII file 726. For example, a devicemanufacture process may include providing the GDSII file 726 to a maskmanufacturer 730 to create one or more masks, such as masks to be usedwith photolithography processing, illustrated as a representative mask732. The mask 732 may be used during the fabrication process to generateone or more wafers 734, such as a silicon on insulator (SOI) wafer, asilicon on silicon (SOS) wafer, or a bulk silicon wafer. For example,the wafers 734 may correspond to the wafer 202 of FIG. 2A or the wafer292 of FIG. 2B, which may be tested and separated into dies, such as arepresentative die 736. The die 736 may include or correspond to the die102 of FIG. 1.

In a particular embodiment, the fabrication process 728 is implementedby a computer including a processor 731 and a memory 733. The memory 733(e.g., a non-transitory computer-readable medium) may includeinstructions that are executable by the processor 731 to cause theprocessor 731 to operate in accordance with at least a portion of any ofthe method 300 of FIG. 3, the method 400 of FIG. 4, the method 500 ofFIG. 5, or any combination thereof. For example, the computer-executableinstructions may be executable to cause the processor 731 to initiateformation of a complementary metal-oxide-semiconductor (CMOS) device.The formation of the CMOS device includes forming a first gate oxide ina first region and in a second region of a wafer, such as a silicon oninsulator (SOI) wafer, a silicon on silicon (SOS) wafer, or a bulksilicon wafer. The CMOS device is further formed by performing firstprocessing to form a second gate oxide in the second region. The secondgate oxide has a different thickness than the first gate oxide. Theformation of the CMOS device also includes forming first gate materialof a first device in the first region and forming second gate materialof a second device in the second region. The first device corresponds to(e.g., is configured to operate in) a first radio frequency (RF) band,and the second device corresponds to (e.g., is configured to operate in)a second RF band that is different from the first RF band.

As another example, the computer-executable instructions may beexecutable to cause the processor 731 to initiate performing acomplementary metal-oxide-semiconductor (CMOS) process to form a firstradio frequency (RF) circuit and a second RF circuit. The first RFcircuit is designed to operate at a first RF band, and the second RFcircuit is designed to operate at a second RF band that is differentfrom the first RF band. The CMOS process includes forming a first RFdevice of the first RF circuit and forming a second RF device of thesecond RF circuit. The first RF device has a first device type and afirst value of a characteristic, and the second RF device has a seconddevice type and a second value of the characteristic. The first devicetype and the second device type are a same device type, and the firstvalue of the characteristic is different from the second value of thecharacteristic.

The die 736 may be provided to a packaging process 738 where the die 736is incorporated into a representative package 740. For example, thepackage 740 may include the single die 736 or multiple dies, such as asystem-in-package (SiP) arrangement. The package 740 may be configuredto conform to one or more standards or specifications, such as JointElectron Device Engineering Council (JEDEC) standards.

Information regarding the package 740 may be distributed to variousproduct designers, such as via a component library stored at a computer746. The computer 746 may include a processor 748, such as one or moreprocessing cores, coupled to a memory 750. A printed circuit board (PCB)tool may be stored as processor-executable instructions at the memory750 to process PCB design information 742 received from a user of thecomputer 746 via a user interface 744. The PCB design information 742may include physical positioning information of a packaged semiconductordevice on a circuit board, the packaged semiconductor devicecorresponding to the package 740 including the die 102 of FIG. 1.

The computer 746 may be configured to transform the PCB designinformation 742 to generate a data file, such as a GERBER file 752 withdata that includes physical positioning information of a packagedsemiconductor device on a circuit board, as well as layout of electricalconnections such as traces and vias, where the packaged semiconductordevice corresponds to the package 740 including the die 102 of FIG. 1.In other embodiments, the data file generated by the transformed PCBdesign information may have a format other than a GERBER format.

The GERBER file 752 may be received at a board assembly process 754 andused to create PCBs, such as a representative PCB 756, manufactured inaccordance with the design information stored within the GERBER file752. For example, the GERBER file 752 may be uploaded to one or moremachines to perform various steps of a PCB production process. The PCB756 may be populated with electronic components including the package740 to form a representative printed circuit assembly (PCA) 758.

The PCA 758 may be received at a product manufacture process 760 andintegrated into one or more electronic devices, such as a firstrepresentative electronic device 762 and a second representativeelectronic device 764. As an illustrative, non-limiting example, thefirst representative electronic device 762, the second representativeelectronic device 764, or both, may be selected from the group of a settop box, a music player, a video player, an entertainment unit, anavigation device, a communications device, a personal digital assistant(PDA), a fixed location data unit, and a computer, into which the die102 of FIG. 1 is integrated. As another illustrative, non-limitingexample, one or more of the electronic devices 762 and 764 may be remoteunits such as mobile phones, hand-held personal communication systems(PCS) units, portable data units such as personal data assistants,global positioning system (GPS) enabled devices, navigation devices,fixed location data units such as meter reading equipment, or any otherdevice that stores or retrieves data or computer instructions, or anycombination thereof. Although FIG. 7 illustrates remote units accordingto teachings of the disclosure, the disclosure is not limited to theseexemplary illustrated units. Embodiments of the disclosure may besuitably employed in any device which includes active integratedcircuitry including memory and on-chip circuitry.

A device that includes the die 102 of FIG. 1, may be fabricated,processed, and incorporated into an electronic device, as described inthe illustrative process 700. One or more aspects of the embodimentsdisclosed with respect to FIGS. 1-6 may be included at variousprocessing stages, such as within the library file 712, the GDSII file726, and the GERBER file 752, as well as stored at the memory 710 of theresearch computer 706, the memory 718 of the design computer 714, thememory 733 of a computer associated with the fabrication process 728,the memory 750 of the computer 746, the memory of one or more othercomputers or processors (not shown) used at the various stages, such asat the board assembly process 754, and also incorporated into one ormore other physical embodiments such as the mask 732, the die 736, thepackage 740, the PCA 758, other products such as prototype circuits ordevices (not shown), or any combination thereof. Although variousrepresentative stages of production from a physical device design to afinal product are depicted, in other embodiments fewer stages may beused or additional stages may be included. Similarly, the process 700may be performed by a single entity or by one or more entitiesperforming various stages of the process 700.

In conjunction with one or more of the described embodiments, anapparatus is disclosed that may include a first radio frequency (RF)component corresponding to (e.g., configured to operate in) a first RFband, and a second RF component corresponding to (e.g., configured tooperate in) a second RF band that is different from the first RF band.The first RF component may include first means for gating a firstchannel. The first means for gating may correspond to the first gate 242or the second gate 262 of FIGS. 2A-B, one or more other devices orcircuits configured to gate the first channel, or any combinationthereof. The first channel may be positioned between first means forsourcing first current to the first channel and first means for drainingthe first current from the first channel. The first means for sourcingmay correspond to one of the S/D implants 210 of FIGS. 2A-B, one or moreother devices or circuits configured to source the first current to thefirst channel, or any combination thereof. The first means for drainingmay correspond to another of the S/D implants 210 of FIGS. 2A-B, one ormore other devices or circuits configured to drain the first currentfrom the first channel, or any combination thereof. The first means forgating the first channel is insulated from first semiconductor means forconducting first charge carriers by a first insulator. The firstsemiconductor means for conducting may correspond to the semiconductinglayer 208 of FIG. 2A, the substrate 294 of FIG. 2B, one or more otherdevices or circuits configured to conduct the first charge carriers, orany combination thereof. The first insulator may correspond to theinsulator material 206 of FIG. 2A, one or more other materialsconfigured to insulate the first means for gating from the firstsemiconductor means for conducting, or any combination thereof.

The second RF component of the apparatus may include second means forgating a second channel. The second means for gating may correspond tothe first gate 242 or the second gate 262 of FIGS. 2A-B, one or moreother devices or circuits configured to gate the second channel, or anycombination thereof. The second channel may be positioned between secondmeans for sourcing second current to the second channel and second meansfor draining the second current from the second channel. The secondmeans for sourcing may correspond to the S/D implants 210 of FIGS. 2A-B,one or more other devices or circuits configured to source the secondcurrent to the second channel, or any combination thereof. The secondmeans for draining may correspond to the S/D implants 210 of FIGS. 2A-B,one or more other devices or circuits configured to drain the secondcurrent from the second channel, or any combination thereof. The secondmeans for gating the second channel is insulated from the secondsemiconductor means for conducting first charge carriers by a secondinsulator. The second semiconductor means for conducting may correspondto the semiconducting layer 208 of FIG. 2A, the substrate 294 of FIG.2B, one or more other devices or circuits configured to conduct thesecond charge carriers, or any combination thereof. The second insulatormay correspond to the insulator material 206 of FIG. 2A, one or moreother materials circuits configured to insulate the second means forgating from the second semiconductor means for conducting, or anycombination thereof. A first thickness of the first insulator isdifferent than a second thickness of the second insulator.

In conjunction with the described embodiments, a method is disclosedthat may include a step for forming a first gate oxide in a first regionand in a second region of a wafer, such as described in the method 300of FIG. 3 at 302, the method 400 of FIG. 4 at 402, 404, described in themethod 500 of FIG. 5 at 504, a deposition process, a lithographyprocess, an etch process, one or more other processes configured to formthe first gate oxide in the first region and in the second region of thewafer, or any combination thereof. The method may also include a stepfor performing first processing to form a second gate oxide in thesecond region, such as described in the method 300 of FIG. 3 at 304, themethod 400 of FIG. 4 at 402, 406, described in the method 500 of FIG. 5at 504, a deposition process, a lithography process, an etch process,one or more other processes configured to perform the first processingto for the second gate oxide in the second region, or any combinationthereof. The method may also include a step forming first gate materialof a first device in the first region and forming second gate materialof a second device in the second region, such as the as described in themethod 300 of FIG. 3 at 302, 304, the method 400 of FIG. 4 at 408,described in the method 500 of FIG. 5 at 508, a deposition process, alithography process, an etch process, one or more other processesconfigured to form the first gate material of the first device in thefirst region and form the second gate material of the second device inthe second region, or any combination thereof. The first devicecorresponds to a first radio frequency (RF) band, and the second devicecorresponds to a second RF band that is different from the first RFband.

Although one or more of FIGS. 1-7 may illustrate systems, apparatuses,and/or methods according to the teachings of the disclosure, thedisclosure is not limited to these illustrated systems, apparatuses,and/or methods. Embodiments of the disclosure may be suitably employedin any device that includes integrated circuitry including memory, aprocessor, and on-chip circuitry.

Those of skill would further appreciate that the various illustrativelogical blocks, configurations, modules, circuits, and algorithm stepsdescribed in connection with the embodiments disclosed herein may beimplemented as electronic hardware, computer software executed by aprocessor, or combinations of both. Various illustrative components,blocks, configurations, modules, circuits, and steps have been describedabove generally in terms of their functionality. Whether suchfunctionality is implemented as hardware or processor-executableinstructions depends upon the particular application and designconstraints imposed on the overall system. Skilled artisans mayimplement the described functionality in varying ways for eachparticular application, but such implementation decisions should not beinterpreted as causing a departure from the scope of the presentdisclosure.

The steps of a method or algorithm described in connection with theembodiments disclosed herein may be embodied directly in hardware, in asoftware module executed by a processor, or in a combination of the two.A software module may reside in random access memory (RAM), flashmemory, read-only memory (ROM), programmable read-only memory (PROM),erasable programmable read-only memory (EPROM), electrically erasableprogrammable read-only memory (EEPROM), registers, hard disk, aremovable disk, a compact disc read-only memory (CD-ROM), or any otherform of non-transient storage medium known in the art. An exemplarystorage medium is coupled to the processor such that the processor canread information from, and write information to, the storage medium. Inthe alternative, the storage medium may be integral to the processor.The processor and the storage medium may reside in anapplication-specific integrated circuit (ASIC). The ASIC may reside in acomputing device or a user terminal. In the alternative, the processorand the storage medium may reside as discrete components in a computingdevice or user terminal.

The previous description of the disclosed embodiments is provided toenable a person skilled in the art to make or use the disclosedembodiments. Various modifications to these embodiments will be readilyapparent to those skilled in the art, and the principles defined hereinmay be applied to other embodiments without departing from the scope ofthe disclosure. Thus, the present disclosure is not intended to belimited to the embodiments shown herein but is to be accorded the widestscope possible consistent with the principles and novel features asdefined by the following claims.

What is claimed is:
 1. A device comprising: a first radio frequency (RF)component on a die, wherein the first RF component includes a firstlightly doped region having a first value of a characteristic, the firstRF component configured to operate in a first RF band associated with afirst frequency; and a second RF component on the die, wherein thesecond RF component includes a second lightly doped region having asecond value of the characteristic that is different from the firstvalue, the second RF component configured to operate in a second RF bandassociated with a second frequency that is different from the firstfrequency.
 2. The device of claim 1, wherein the characteristic includesa profile, a dopant type, or a dopant concentration.
 3. The device ofclaim 1, wherein the first lightly doped region has a larger profilethan the second lightly doped region.
 4. The device of claim 1, whereina first molecular weight of a first dopant in the first lightly dopedregion is greater than a second molecular weight of a second dopant inthe second lightly doped region.
 5. The device of claim 1, wherein afirst dopant concentration of a first dopant in the first lightly dopedregion is greater than a second dopant concentration of a second dopantin the second lightly doped region.
 6. The device of claim 1, whereinthe second RF component is fabricated by a process that includes forminga layer of a first gate oxide, removing a portion of the first gateoxide from a region of the die, and forming a layer of a second gateoxide in the region.
 7. The device of claim 1, wherein the first RFcomponent and the second RF component comprise semiconductor devicesthat are integrated in the die.
 8. The device of claim 1, wherein thefirst RF component includes a first halo region having a third value ofa second characteristic, and the second RF component includes a secondhalo region having a fourth value of the second characteristic that isdifferent from the third value.
 9. A device comprising: a first radiofrequency (RF) component on a die, wherein the first RF componentincludes a first halo region having a first value of a characteristic,the first RF component configured to operate in a first RF bandassociated with a first frequency; and a second RF component on the die,wherein the second RF component includes a second halo region having asecond value of the characteristic, wherein the second value isdifferent from the first value and the second RF component is configuredto operate in a second RF band associated with a second frequency thatis different from the first frequency.
 10. The device of claim 9,wherein the characteristic includes a profile, a dopant type, or adopant concentration.
 11. The device of claim 9, wherein the first haloregion has a larger profile than the second halo region.
 12. The deviceof claim 9, wherein a first molecular weight of a first dopant in thefirst halo region is greater than a second molecular weight of a seconddopant in the second halo region.
 13. The device of claim 9, wherein afirst dopant concentration of a first dopant in the first halo region isgreater than a second dopant concentration of a second dopant in thesecond halo region.
 14. The device of claim 9, wherein the second RFcomponent is fabricated by a process that includes forming a layer of afirst gate oxide, removing a portion of the first gate oxide on a regionof the die, and forming a layer of a second gate oxide on the region.15. The device of claim 9, wherein the first RF component and the secondRF component comprise semiconductor devices that are integrated in thedie.
 16. A method comprising: performing, on a wafer, a complementarymetal-oxide-semiconductor (CMOS) process to form a first radio frequency(RF) circuit and a second RF circuit, the first RF circuit configured tooperate in a first RF band associated with a first frequency, the secondRF circuit configured to operate in a second RF band associated with asecond frequency that is greater than the first frequency, whereinperforming the CMOS process comprises: forming a first RF device of thefirst RF circuit, the first RF device having a first device type and afirst value of a characteristic; and forming a second RF device of thesecond RF circuit, the second RF device having a second device type anda second value of the characteristic, wherein the first device type andthe second device type are a same device type, and wherein the firstvalue of the characteristic is different from the second value of thecharacteristic.
 17. The method of claim 16, wherein the device type isone of a power amplifier, a switch, or a low noise amplifier, andwherein the characteristic is associated with an oxide thickness, achannel length, a spacer profile, a halo profile, or a lightly dopedprofile.
 18. The method of claim 16, wherein performing the CMOS processis initiated by a processor integrated into an electronic device. 19.The method of claim 16, wherein forming the first RF device comprises:forming a first gate oxide in a first region and in a second region of awafer, the first gate oxide having a first thickness; and forming firstgate material in the first region.
 20. The method of claim 19, whereinforming the second RF device comprises: performing first processing toform a second gate oxide in the second region, the second gate oxidehaving a second thickness that is less than the first thickness; andforming second gate material of in the second region.